Design And Reuse SoC News Alert

January 18, 2005

Michael,
Welcome to issue of January 18, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: eASIC, Corp.

NRE-free Structured ASIC

ASIC-like unit-cost, power and performance

FPGA-like ease of design (SRAM-LUT)

Flexible exchange between logic and distributed memory

No minimum volume required

Turnaround: < 2 weeks

Built-in clock tree, BIST, scan chain and power distribution

Easy post-fabrication debug - LUT reload

Variety of configurable I/Os

Embedded 8051 microcontroller

SuperMAP III Coprocessor for PKI (Synthesizable Configuration) from M-Systems

1 to 40Mhz Crystal Oscillator from ChipIdea Microelectronics

Silicon-proven IP for ARC4 encryption and decryption from SafeNet

Quad Voice CODEC compliant to ITU-T G.712 from Cologne Chip AG

CEVA-TeakLite-II, a Low power, single Multiply-Accumulate (MAC), 16-bit fixed point DSP core from Ceva, Inc.

AAC Decoder for Texas Instruments DSP from Ateme

Wanted IPs :

802.16.4 Baseband & MAC IP

Is IP Quality Achievable, Measurable and Enforceable through the Design Chain?

Reducing false errors in clock-domain crossing analysis

High-Speed Serial fully digital interface between WLAN RF and BB chips

FPGA-Based DPLL Approach Delivers Wide-Lock Range

Intellectual Quandary

IP/SOC PRODUCTS

ARC International and Magma Deliver Customer-Proven Reference Methodology for the ARC 600 Configurable Microprocessor Core

OCP-IP Unveils CoreCreator 4.0

QualCore Logic Announces Availability of 15 Silicon-Validated Analog IP Cores, Special I/Os for Graphics, Memory Interface Applications

PACT announces the Smart Media XPP Package for Multi-Standard Video Codecs

STRUCTURED ASIC

LSI Logic Sets New Logic and Memory Standard with RapidChip Integrator2 Family

DEALS

Silterra Adopts HPL Technologies TechXpress IP to Accelerate Development for 0.13um CMOS Process

Tensilica's Xtensa LX Processor Licensed by NVIDIA

Tensilica Xtensa Processor Powers World's First Digital Broadcast-Enabled Mobile Phone From LG Electronics

ChipIdea Mixed-Signal IP Enables Haier-IC SoC products Fast Time-to-Market and High Production Yield

BUSINESS

TTPCom Plans 300% Expansion of Engineering Facilities in China

Cadence Augments Verification Solution and Expertise Through Acquisition of Verisity

Gaisler Research AB and Gleichmann & Co. Electronics GmbH signs agreement covering the use, marketing and sales of the LEON processor

Electronic Design Technology e.K. signed an agreement to distribute Digital Core Design's VHDL and Verilog high quality synthesizable IP cores in Germany, Austria, Switzerland and Italy

FINANCIAL RESULTS

Mentor Graphics Reports Preliminary 2004 Results;Fourth Quarter Revenue and Bookings Hit Records on 40% Bookings Growth

PEOPLE

Rambus Announces Executive Management Changes

EMBEDDED SYSTEMS

Tharas Systems announces Axis replacement program

MIPS Technologies and Third-Party Developers of VoIP Solutions Enable Low-Cost, Multi-Channel Voice on a Single Chip

FPGA/CPLD

Xilinx Planahead v2.2 Tool Delivers Up To 2X Performance Boost And 50% Design Cycle Reduction For Virtex-4 FPGAs

FABLESS

Analysis: Fabless to benefit as foundries face tough Q1

Innova Card, a fabless semiconductors company specialized in the design and development of secure solutions for smart card terminals, raises Euros 3.5 million with historical shareholders, Innovacom, LC Capital and Siparex Ventures

EDA

How ESL becomes a business imperative

OTHER

Faraday successfully cracks the Ethernet 10/100 niche market

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento

DesignCon 2005
Santa Clara, CA
Feb. 1-2, 2005
Booth 603
Contact D&R

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